The present invention relates to a power fluctuation inhibiting device, and more particularly, to a power fluctuation inhibiting device for suppressing fluctuation of power supply voltage in a semiconductor device.
Semiconductor devices incorporated in recent portable electronic equipment are configured to function in a power down mode in order to reduce power consumption. Internal circuits stop operating during the power down mode to reduce power consumption. In a conventional semiconductor device, the load applied to the power supply fluctuates when the semiconductor device shifts between the power down mode and a normal mode. This causes the power supply voltage to fluctuate. Such power fluctuation may result in erroneous functioning of circuits. Thus, the fluctuation of power supply voltage must be inhibited.
Japanese Laid-Open Patent Publication No. 11-55947 describes a power supply device that supplies power to an air conditioner. In accordance with fluctuations in the load applied to the air conditioner, which functions as a load circuit, the power supply device inhibits power fluctuation by opening and closing a switch of a converter circuit. However, the power supply device cannot sufficiently follow complicated load fluctuations. Accordingly, even if the technical concept of the power supply device is applied to a semiconductor device, power fluctuations cannot be inhibited by following load fluctuations of multiple load circuits.
Japanese Laid-Open Patent Publication No. 10-90370 describes a technology that detects the operation rate of a pulse generation circuit, which functions as a load circuit of a power supply, and operates a current consumption circuit based on fluctuations in the operation rate to reduce transient current. However, it is difficult to match the timing at which the operating rate of the pulse generation circuit fluctuates with the timing for operating the current consumption circuit. It is also difficult to offset the fluctuated amount of the current consumed by the pulse generation circuit with the value of the current consumed by the current consumption circuit.
Accordingly, deviation of the operating timing of the current consumption circuit or an inappropriate value of the current consumed by the current consumption circuit may result in power fluctuation.
FIG. 1 illustrates power fluctuations that occur when activating and inactivating internal circuits in a prior art semiconductor device. For example, when multiple analog circuits start to operate as a first control signal CS1 goes low, the power supply voltage Vs fluctuates.
The power supply voltage Vs also fluctuates when multiple digital circuits start to operate as a second control signal CS2 goes high. Further, when the first and second control signals CS1, CS2 synchronously inactivate the analog and digital circuits, the power supply voltage Vs fluctuates.
FIG. 2 is a block circuit diagram showing a prior art device that inhibits fluctuation of the power supply voltage Vs. As shown in FIG. 2, the power supply voltage Vs is supplied to two load circuits 1a, 1b via switch circuits 2a, 2b, respectively. An activation signal AC1 opens and closes a switch circuit 2a. The delay circuit 3 delays an activation signal AC1 to generate an activation signal AC2 that opens and closes the switch circuit 2b. The load circuits 1a, 1b are activated and inactivated in an asynchronous manner. This inhibits fluctuation of the power supply voltage Vs.
FIG. 3 illustrates a specific example of the load circuit shown in FIG. 2. The load circuit is a current mirror circuit that includes transistors Tr1–Tr3. When a switch circuit 4a goes on and a switch circuit 4b goes off, the transistors Tr1, Tr2 function as a current mirror circuit. When the switch circuit 4a and a switch circuit 4c go on and a switch circuit 4d goes off, the transistors Tr2, Tr3 function as a current mirror circuit.
The switch circuit 4a receives an activation signal AC3. The switch circuit 4c receives an activation signal AC4, which is generated by delaying the activation signal AC3 with a delay circuit 5a. The switch circuit 4b receives an activation signal AC5, which is generated by inverting the activation signal AC3 with an inverter circuit 6. The switch circuit 4d receives an activation signal AC6, which is generated by delaying the activation signal AC5 with a delay circuit 5b. 
The switch circuit 4c goes on after the switch circuit 4a goes on. Thus, the transistors TR2, TR3 start to function as a current mirror circuit after the transistors Tr1, Tr2 start to function as a current mirror circuit. To inactivate the current mirror circuits, after inactivating the switch circuit 4a and activating the switch circuit 4b, the switch circuit 4c is inactivated and the switch circuit 4d is activated.
Accordingly, after the transistors Tr1, Tr2 stop functioning as a current mirror circuit, the transistors Tr2, Tr3 stop functioning as a current mirror circuit. The transistors Tr1, Tr2 and the transistors Tr2, Tr3 are activated and inactivated in an asynchronous manner. Thus, fluctuation of the power supply voltage is inhibited.
In the circuit of FIG. 3, the switch circuits 4a–4d are especially required to offset the operating timing of the current mirror circuits. However, the switch circuits 4a, 4c may especially fluctuate the gate voltage of the transistors Tr1, Tr3. Thus, when the current mirror circuit requires accuracy, the switch circuits 4a–4d cannot be employed.